Verification Methodology Manual for SystemVerilog

Provides a reference methodology that can be adopted by designers and verification engineers for all types of System-on-a-Chip projects. With authors from ARM(R) and Synopsys(R), it combines ARMs expertise in the verification of complex, configurable IP from transaction-level SystemC to timing-critical register-transfer level (RTL) implementation, and Synopsys strength in delivering an integrated RTL and system verification platform, including tools and verification IP. Verification Methodology Manual for SystemVerilog describes SystemVerilog language features relevant to functional verification and provides a blueprint for a robust, scalable verification architecture based on industry best practices. This book also specifies a standard set of libraries for assertions and commonly used verification functions, such as stimulus generation, simulation control and coverage analysis, to help implement the recommended methodology. The Manual can help SoC development teams achieve faster and more effective design verification. It also guides verification IP providers to follow a consistent and well-documented architecture, enabling end users to easily integrate verification IP from multiple sources.