Reconfigurable Computing: Architectures

For manyyears, the idea of recon?gurablehardwaresystems hasrepresentedthe Holy Grail for computer systemdesigners.It has been recognizedfor a long time that the microprocessor provides high ?exibility but at a very low performance merit in terms of MIPS/W or other such measures. Recon?gurable systems are thus attractive as they can be con?gured to provide the best match for the computational requirements at that speci?c time, giving much better area - speed - power performance. However, the practicalities of achieving such a recon?gurable system are - merous andrequirethe developmentof: suitable recon?gurablehardwareto s- portthe dynamicbehavior;programmingtoolsto allowthe dynamicbehavior of the recon?gurability to be modelled; programming languages to support rec- ?guration;andveri?cationtechniquesthatcandemonstratethatrecon?guration hashappenedcorrectlyateachstage.Whiletheproblemsaremany, theexistence and development of technologies such as the multi-core processor architecture, recon?gurable computing architectures, and application-speci?c processors s- gest there is a strong desire for recon?gurable systems. Moreover, FPGAs also provide the ideal platforms for the development of such platforms. The major motivation behind the International Workshop on Applied - con?gurable Computing (ARC) series is to create a forum for presenting and discussing on-going research e?orts in applied recon?gurable computing. The workshop also focuses on compiler and mapping techniques, and new recon- urablecomputingarchitectures.Theseriesofeditionsstartedin2005inAlgarve, Portugal, followed by the 2006 workshop in Delft, The Netherlands, and last years workshop in Mangaratiba, Rio de Janeiro, Brazil. As in previous years, selectedpapershavebeenpublished asa SpringerLNCS(LectureNotes in C- puter Science) volume.