Symbolic Analysis and Reduction of VLSI Circuits

The IC industry, including digital and analog circuit design houses, electrical design automation software vendors, library and IP providers face significant challenges in designing nanometer VLSI systems. The design productivity gap between nanometer VLSI technologies and todays design capabilities mainly comes from the exponentially growing complexity of VLSI systems due to relentless pressures for higher integration. The physical effects on the performance and reliability of these systems are becoming more pronounced. So efficient modelling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms. Symbolic Analysis and Reduction of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation, which allow analysis and modeling of much larger circuitry than ever before.