Constraint-Based Verification

As the complexity and miniaturization of electronic hardware advances, more time and money is actually now spent on testing and verification than in the preliminary design stage. This practical-oriented guidebook covers both the fundamentals and the techniques of constraint-based testbench automation. The book compares and contrasts constraint-based verification with traditional testbench approaches: test generation (a key concept), simulation monitoring, and coverage. Related aspects of verification languages such as e/vera/PSL/OVL/SVA are also covered. On the technical side, state-of-the art algorithms of test generation, performance optimization, and randomization are explained.